Introduction.
TILE-Gx is Tilera's second generation high performance manycore(36/72/100 core) processor. It's with VLIW architecture, up to 3 issues each cycle, 64 64-bit general purpose registers, 64-bit address space and 64-bit instructions. TILE-Gx has load-store architecture ISAs. You can find more hardware details here http://www.tilera.com/scm/docs/index.html.
Clang/LLVM support for Tilera TILE-Gx architecture has reached a quite stable status. It passed llvm regression test, test-suite, and clang/llvm bootstrap. It's open for anyone's access, please have a try. We appreicate all your feedbacks.
Getting Source Code
$ git clone https://github.com/tilera/llvm.git
$ cd llvm/tools/
$ git clone https://github.com/tilera/clang.git
Build From Source
$ mkdir BUILD_ROOT
$ cd BUILD_ROOT
$ SOURCE_ROOT/configure --enable-targets=tilegx
$ make ENABLE_OPTIMIZED=1 -j40 (for cross build on X86, -j4...)
Clang/LLVM will generate huge binary, so the linking stage is very long. One tip to fast the linking is uing GOLD linker, it's 3x faster than GNU ld, and supported on TILE-Gx already. To build llvm using GOLD linker, you need to specify the extra -B option to relocate the linker used:
$ make ENABLE_OPTIMIZED=1 CFLAGS+="-B/PATH_TO_GOLD_BIN/" CXXFLAGS+="-B/PATH_TO_GOLD_BIN/" -j40
Usage
On TILE-Gx native environment, is's simple, just as what has been documented on llvm manual.
Compile .c directly into executable:
$ clang -o hello.tilegx hello.c
Compile .c into llvm IR:
$ clang -S -emit-llvm -o hello.ll hello.c
Compile .ll into .s or JIT .ll:
$ llc/lli hello.ll
For cross compile on X86, you need to specify target options.
Clang:
$ clang -target tilegx -o hello.tilegx hello.c
llc/lli:
$ llc/lli -march=tilegx hello.ll
You can use --help and --help-hidden for more options.
Backend Status
Unknown | No support | Partial Support | Complete Support |
---|---|---|---|
? | N | P | Y |
Here is the status table:
Feature | Status |
---|---|
is generally reliable | Y |
pic/tls | Y |
assembly parser | P |
disassembler | N |
inline asm | P |
mc layer | Y |
mc jit | Y |
tail calls | N |
hard float | Y |
simd | Y |
We are trying hard to implement all those left features. And we are implementing the following:
- tail call optimization.
- scheduler improvements.
Support or Contact
Having trouble with running llvm on TILE-Gx? Please don't hesitate to send us email walt@tilera.com and we’ll help you sort it out.